The present invention relates generally to the field of integrated circuit (IC) design, and more particularly to placement and optimization of components during the physical design stage of IC design.
IC design can be broken down into multiple stages of design. In the initial stages of IC design, circuit specifications, architectural design, and logic design are completed. The completion of the logic design stage typically results in a computer software model that describes the structure, design, and operation of the IC. The model can be written in one or more of a variety of computer readable languages, commonly called a hardware description language (HDL). A common hardware description language is the very high speed integrated circuit (VHSIC) hardware description language (VHDL). The HDL model can include descriptions of certain areas of the IC which are considered “timing critical,” which means that the time frame in which information is conveyed through the circuit in the form of signals needs to be designed in an accurate manner to ensure the correct operation of the IC as a whole.
In the physical design stage of IC design, engineers use the HDL model to generate physical parameters of the components that make up the IC. Physical design uses electronic design automation (EDA) tools to model the physical attributes of the IC. EDA tools use two main strategies to perform physical design: flat design and hierarchical design. In a flat design, the EDA tool places all of the components in the IC at once. Hierarchical design presents a divide and conquer approach in which certain subsets of the IC components are placed separately and later inserted into the complete parent design. The subsets of the circuit that are modeled separately are called “child blocks” and, when built, will be self-contained as a single unit having one or more pins connecting the child block components to the parent block components.